1. Field of the Invention
The present invention relates to an failsafe interface circuit for the input and output of digital signals and a method for the failsafe operation of an interface circuit.
Currently, a variety of concepts for digital interface logic circuitry is known. Early concepts are diode-transistor logic DTL, transistor-transistor logic TTL and emitter coupled logic ECL which concepts are used with digital logic circuits as well as digital signaling between circuits and circuit boards.
Further approaches are based on MOS-processes (metal oxide semiconductor processes) which allow for advantages as higher packaging density or lower power consumption. Due to these advantages the MOS-processes now are widely used for very large scale integrated circuits such as semiconductor memories, microcomputers and circuits for the digital signal processing.
In particular the so called CMOS-technology wherein MOS-transistors of both the n-channel type and the p-channel type, i.e. PMOS-transistors and NMOS-transistors are integrated on a single chip has been proven to be extremely useful for such applications. One reason is that the combination of PMOS- and NMOS-transistors allows to achieve almost no zero signal current and a significantly reduced power loss.
Further, the transfer characteristics of circuits constituting switching circuits can be very steep in case PMOS- and NMOS-transistors are actuated reciprocally. The CMOS-technology allows for a relatively low output resistance defined through the resistance of the drain source path of the respective PMOS- and NMOS-transistors. This is a further reason why CMOS-technology has gained significant importance for the design of digital circuitry.
Typical applications are interface circuits for the transmission of digital data with a high transfer rate, e.g., the differential transmission and reception of digital data using a pair of transmission lines. Here, approaches like differential positive emitter coupled logic DPECL, low voltage differential signaling LVDC and grounded low voltage differential signaling GLVDS are used. All these approaches use differential signaling to keep differential voltages across a pair of transmission lines as low as possible. This in turn keeps the power to be transmitted over these transmission lines having low impedances within reasonable limits.